1. Field of the Invention
The present invention relates to ferroelectric memory devices which store data by use of ferroelectric capacitors in a nonvolatile way. This invention also relates to read control methodology for use with the nonvolatile ferroelectric memory devices.
2. Description of Related Art
Ferroelectric memory chips store binary data nonvolatilely in a way depending upon the magnitude of a remnant polarization of a ferroelectric capacitor. Prior known ferroelectric memories include memory cells, each of which is generally made up of a serial combination of one ferroelectric capacitor and one transistor in a similar manner to that in currently available dynamic random access memory (DRAM) chips. However, unlike DRAMs, ferroelectric memories are designed to store data in the form of the magnitude of a remnant polarization so that a need is felt to drive a plate line in order to read signal charge out of a memory cell onto a bit line associated therewith. Due to this, in prior art ferroelectric memories, plate-line drive circuitry requires the consumption of an increased chip area.
In contrast, an advanced ferroelectric memory cell array scheme capable of lessening the area of such plateline drive circuitry has been proposed by Takashima et al. This architecture is such that a memory cell, called unit cell, consists essentially of a parallel combination of one cell transistor (T) and one ferroelectric capacitor (C) with its both ends coupled to a source and a drain of the transistor. A plurality of such 1T/1C memory cells are connected in series into the form of a chain to provide a cell group, known as a cell block, as disclosed in D. Takashima et al., “High-Density Chain Ferroelectric Random Access Memory (CFRAM),” in Proc. VLSI Symp. June 1997, pp. 83–84. In ferroelectric memory chips of the type using such “TC-parallel cell-unit series-connected” configuration, a number—e.g. eight (8)—of unit cells are permitted to share a plateline drive circuit, thus enabling achievement of higher integration densities of on-chip cell arrays.
Practically the data of a ferroelectric memory is as follows. When a unit cell's ferroelectric capacitor is in a positive remnant polarization state, the data stored therein is a logic “1” (one); when in a negative remnant polarization state, a logic “0” (zero). The data readout principles in this case are as shown in FIGS. 12A and 12B. As apparent from viewing a hysteresis loop shown in FIG. 12A, a logic “1” data bit is read by applying a voltage to the ferroelectric capacitor in a presently selected cell from a plate line associated therewith. At this time the data is read destructively while accompanying a polarization reversal. After completion of the “1” data readout, the cell data temporarily becomes a logic “0.” Thereafter, the ferroelectric capacitor is applied a reverse voltage in a way responsive to a read voltage obtainable on a bitline. This reverse voltage application causes the capacitor to again experience a polarization reversal, resulting in “1” data is restored or rewritten back thereinto. Reading of “0” data shown in FIG. 12B is nondestructive readout accompanied with no polarization reversal. In this event no voltage is applied to the ferroelectric capacitor even after the readout, resulting in “0” being rewritten without requiring any extra procedures.